Low-power distributed arithmetic architectures using nonuniform memory partitioning

1. I N T R O D U C T I O N A common operation in digital signal processing (DSP) is computing the inner product of two vectors. Distributed arithmetic (DA) [8] has been used to compute the inner product because of the efficiency of DA architectures. In a DA architecture, the multiplier is eliminated by employing a memory to store linear combinations of the coefficients. Figure 1 shows one possible DA-based implementation of a 4-tap FIR filter. The memory addresses are formed by grouping bits in the same bit position from successive input samples. The input is shifted in one bit a t a time into the register containing z(n) . The output is available once every B clocks (where B is the input precision) from the accumulator. The size of the memory for a k-tap filter is 2k words. It is possible to reduce the memory size to Zk-' words by employing extra logic [8]. In this paper, we will concentrate on the architecture in Figure 1, though all our techniques are applicable to the architecture with memory of size 2k-' words. In a DA-based filter, power is dissipated in the shift register, memory, adder, shifter, and the accumulator. Since the memory size increases exponentially with the number of taps and the power dissipation in a memory increases with its size, a considerable amount of the total power dis-